1. Field of the Invention
The present invention relates to an electrically erasable programmable read-only memory (E.sup.2 PROM) and, particularly, to an E.sup.2 PROM array which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows.
2. Description of the Prior Art
A basic semiconductor memory array consists of a matrix of rows and columns of electrical conducting paths formed on a semiconductor chip. The conducting paths of the matrix do not physically intersect but rather are interconnected at the cross-over points by memory cells. Each memory cell stores a bit of binary data, i.e., either a "0" or a "1". Whether a "0" or a "1" is stored is based upon whether or not the cell conducts. Binary data stored in the memory array is read from an individual memory cell by applying a voltage to the conducting row containing the selected cell and monitoring the conducting column of that cell to determine whether it is drawing current.
In one type of memory array, the conducting paths are interconnected by memory cells which are permanently altered during fabrication to be either conducting or nonconducting. That is, the binary data to be stored in each cell is inalterably encoded during the fabrication process. For this reason, such an array is known as a read-only memory (ROM). Since alteration of the memory content of a ROM requires expensive redesign, it is impractical to incorporate ROMs into equipment having short production runs. To compensate for this inherent deficiency, a programmable read-only memory (PROM) was developed.
A typical PROM consists of a matrix of conducting paths similar to that of a ROM. Rather than utilizing the permanently altered memory cells which are definitive of a ROM for interconnecting the cross-over points of the matrix, a PROM interconnects the cross-over points by memory cells which include an alterable element such as a fuse. Thus, each cell may be selectively programmed. PROMs are usually shipped to the end user in an unencoded state. Each bit of binary data comprising the memory information to be stored in the array is then programmed into the array by altering the appropriate memory cells. This selectively programmable feature allows a standard PROM design to function as a memory array in a variety of applications. PROMs, however, are limited in that once the memory cells of a PROM have been programmed, they, like the cells of a ROM, cannot be altered. The solution to this limitation is provided by the erasable PROM (E-PROM).
Conventional E-PROMs maintain the general matrix structure of the ROM and PROM. The interconnecting memory cells of an E-PROM are floating gate field effect transistors. In floating gate field effect transistors, the voltage of the transistor's control gate is capacitively coupled in series with the floating gate rather than directly to the underlying channel as is the case in conventional field effect transistors. Because of this capacitive coupling, the presence of charge on the floating gate alters the threshold voltage of the transistor as seen by the control gate. This feature allows binary data to be stored in the transistor as the presence or absence of charge on the floating gate.
An E-PROM memory cell with its floating gate uncharged conducts at a normal threshold voltage, representing one binary state. The binary state of the cell may be changed by injecting charge into the floating gate. As stated above, the charge on the floating gate raises the normal threshold voltage of the transistor. Thus, the memory cell will not conduct unless the control gate voltage is sufficient to overcome the charge on the floating gate. Therefore, the binary state of the cell may be read by applying a voltage to the control gate of the cell which is between the normal threshold voltage of an uncharged cell and the increased threshold voltage of a charged cell. The cell is then monitored to determine whether it is conducting or non-conducting.
In a conventional floating gate memory cell, the floating gate is charged by energizing the electrons in the channel of the underlying field effect transistor. When the electrons gain sufficient energy, they overcome the energy barrier between the substrate of the cell and the oxide insulator which surrounds the floating gate and penetrate the oxide. Once the electrons penetrate the oxide, they are attracted to the floating gate which is capacitively coupled with a positive potential applied to the control gate.
The advantage of an E-PROM is that the charged cells of an E-PROM array may be erased by removing stored electrons from the floating gate. This is done by exposing the entire array to ultraviolet light through an overlying quartz window. Photons are absorbed by the electrons held by the floating gate of each charged cell in the array. The cell discharges as the electrons become energized, leave the floating gate through the surrounding oxide insulator and are drawn either to the control gate or to the substrate.
The disadvantage of UV erasable E-PROMs is that erasure is nonselective. Because the entire E-PROM structure is exposed to ultraviolet light, complete erasure of all of the memory cells in the matrix is required before the array can be reprogrammed. Thus, while UV-erasable E-PROMs are adequate for off-board reprogramming, they do not fill the need in applications which require numerous alterations of the stored data without removing the memory from its system environment.
More recently, electrically erasable PROMs (E.sup.2 PROM) have been developed. E.sup.2 PROMS provide for selective erasure and, thus, for in-circuit programming. In addition, E.sup.2 PROMs are inherently more convenient and less costly to use since they require no external ultraviolet light source for erasure. E.sup.2 PROMs also offer the further advantages of low power consumption and low current requirements for both erasure and programming.
A conventional floating gate E.sup.2 PROM memory cell is divided into two regions. A first select region provides access to the second region of the cell. The second region provides binary data storage. The storage region is a floating gate field effect transistor. The storage region cannot be accessed for programming, reading or erasure unless the select region of the same cell is activated.
Charge is transferred to and from the floating gate of the storage region by the mechanism of tunneling. Tunneling is the movement of electrons through a thin portion of normally thick insulator material, typically silicon oxide, which separates the floating gate from the substrate of the transistor. Normal insulator thickness is about 500 Angstroms. The thin oxide utilized for tunneling is usually 200 Angstroms or less thick.
In one type of E.sup.2 PROM floating gate memory cell, the select region and the storage region of the cell are distinctly formed in adjacent oxide-isolated portions of a semiconductor chip. The select region is a conventional field effect transistor. The storage region is a floating gate field effect transistor. The floating gate of the storage transistor is insulated from the underlying substrate by the normal gate oxide and by a thin length of oxide which is about 200 Angstroms or less thick. The thin oxide is formed over the N-doped drain region of the storage transistor. The control gate of the storage transistor is polysilicon.
The above-described memory cell may be utilized in an E.sup.2 PROM array which provides for individual byte alteration. According to the byte-alterable design, rows of eight-cell bytes are arranged side-by-side in a plurality of vertical groups. The control gates of the eight storage transistors of the memory cells of a selected byte are connected to a horizontal storage transistor conducting path which is unique to that byte. All of the storage transistor conducting paths of a vertical group of bytes are connected to a vertical byte access conducting path which is unique to that vertical group. A conventional field effect byte access transistor is located between the vertical byte access conducting path and the first control gate of each eight-cell byte. The control gates of the select transistors of all bytes in a selected horizontal row in the array are connected to a horizontal select transistor conducting path which is unique to that row. The control gate of each byte access transistor in the selected row is connected to the select transistor conducting path for that row. The drains of the select transistors of a selected column of cells in the array are connected to a vertical conducting path which is unique to that column. The select and storage transistors of an individual memory cell in the array are connected in series such that when both transistors are turned on, they sink current from the vertical conducting path connected to the drain of the select transistor of that cell.
Before a byte of the above-described array is reprogrammed, all storage transistors of the selected byte are erased by returning them to a charged state. To accomplish this, both the select transistor conducting path for the horizontal row containing the selected byte and the storage transistor conducting path for the selected byte are raised to high voltage. That is, for each memory cell of the selected byte, both the control gate of the select transistor and the control gate of the storage transistor are high. This requires that the vertical byte access conducting path for that group of bytes be at high potential so that the byte access transistor for that byte is turned on. All of the remaining vertical conducting paths of the array are grounded. This condition forces electrons through the tunnel oxide of each storage transistor of all memory cells in the selected byte to change the floating gate of each transistor. Thus, all of the memory cells of the selected byte are nonconducting when a read voltage is applied.
Information is written into the selected byte by selectively discharging cells. This is done by grounding the storage transistor conducting path for the selected byte while maintaining the select transistor conducting path for that byte at high potential. Simultaneously, high voltage is applied to the vertical conducting path connected to the drains of those individual cells of the selected byte in which it is desired to write. This causes the floating gates of these cells to discharge. The vertical conducting paths for the remaining cells in the selected byte are maintained at ground. Thus, the charged state of these remaining cells is unchanged. The control gates of the select transistors for non-selected bytes are grounded to prevent the programmed storage transistors in the unselected bytes from discharging.
Reading of binary data from a memory cell of the above-described array is accomplished by applying a positive bias to the control gate of both the select and storage transistor of a cell. A cell having a discharged floating gate will conduct while a cell having a charged floating gate will not conduct.
In another type of floating gate E.sup.2 PROM memory cell, the select region and the storage region are formed together in a single oxide-isolated portion of a semiconductor chip. A polysilicon floating gate is formed over one side of the active region to define the storage region of the cell. The floating gate is isolated from a p-type well beneath it by the normal gate oxide and by a length of thin oxide. An aluminum control gate is formed over the floating gate. The control gate extends beyond the floating gate and over the other side of the active region to define the select region. N-doped regions are formed in the underlying p-type well adjacent both edges of the control gate to serve as source and drain. The aluminum control gate is separated from the floating gate by a layer of silicon nitride/silicon oxide. The silicon nitride enhances the capacitive coupling between the control gate and the floating gate. The p-type well is common to all memory cells of the array.
This type of E.sup.2 PROM memory cell is erased as electrons are discharged from the polysilicon floating gate to the underlying p-type well. This is accomplished by first grounding the control gate of the cell and then applying high voltage to the p-type well. This causes electrons to tunnel from the floating gate, through the thin oxide and to the p-type well, causing the floating gate of the storage transistor to acquire a net positive charge. By relying on raising the potential of the entire p-type well for erasure, however, this type of E.sup.2 PROM foregoes individual cell control.
To write binary data into an erased cell, the p-type well is grounded. The drain is connected through a load resistance to a high voltage. The source of the storage transistor is connected either to a high voltage or to ground depending upon the type of binary data to be stored. To initiate writing, the control gate of the selected cell is raised to high voltage. If the source is also at high voltage, the select region of the cell prevents electrons from flowing through the channel layer and the surface of p-type well beneath the floating gate becomes depleted of electrons. Since, under these conditions, only a small potential difference exists between the surface of the p-type well and the floating gate, no electrons tunnel into the floating gate, there is no change in the potential of the floating gate and the memory cell remains in an erased state.
In contrast, if the source potential is low, then the select region allows electrons to flow. This causes the surface potential under the floating gate to drop low. Electrons from the channel inversion layer pass through the thin oxide and into the floating gate, causing it to acquire a net negative potential.
To the control gate, the charging and discharging of the floating gate look like changes in the threshold voltage of the storage region of the cell. Thus, the binary state of the cell is read by comparing the conductance of the selected memory cell with the conductance of a reference cell.